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HIGH-SPEED 32/16K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM
Features

IDT709279/69S/L
True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access - Commercial: 6.5/7.5/9/12/15ns (max.) - Industrial: 12ns (max.) Low-power operation - IDT709279/69S Active: 950mW (typ.) Standby: 5mW (typ.) - IDT709279/69L Active: 950mW (typ.) Standby: 1mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pin Counter enable and reset features

Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports - 4ns setup to clock and 1ns hold on all control, data, and address inputs - Data input, address, and control registers - Fast 6.5ns clock to data out in the Pipelined output mode - Self-timed write allows fast cycle time - 10ns cycle time, 100MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility TTL- compatible, single 5V (10%) power supply Industrial temperature range (-40C to +85C) is available for selected speeds Available in a 100-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/WL UBL CE0L CE1L LBL OEL
1 0 0/1 1 0 0/1
R/WR UBR CE0R CE1R LBR OER
FT/PIPEL I/O8LI/O15L I/O0L-I/O7L
0/1
1b 0b b a 1a 0a
0a 1a
a b 0b 1b
0/1
FT/PIPER I/O8R-I/O15R
, ,
I/O Control
I/O Control I/O0R-I/O7R
A14L(1) A0L CLKL ADSL CNTENL CNTRSTL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg.
A14R(1) A0R CLKR ADSR CNTENR CNTRSTR
3243 drw 01
NOTE: 1. A14X is a NC for IDT709269.
JUNE 2004
1
(c)2004 Integrated Device Technology, Inc. DSC-3243/13
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
The IDT709279/69 is a high-speed 32/16K x 16 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times.
Description
With an input data register, the IDT709279/69 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 950mW of power.
Pin Configurations(2,3,4)
01/15/04
Index
A9L A10L A11L A12L A13L A14L(1) NC NC NC LBL UBL CE0L CE1L CNTRSTL VCC R/WL OEL FT/PIPEL GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
A8L A7L A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL GND ADSR CLKR CNTENR A0R A1R A2R A3R A4R A5R A6R A7R A8R
IDT709279/69PF PN100-1(5) 100-Pin TQFP Top View(6)
51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A9R A10R A11R A12R A13R A14R(1) NC NC NC LBR UBR CE0R CE1R , CNTRSTR GND R/WR OER FT/PIPER GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R
I/O9L I/O8L VCC I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/OIL I/O0L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R VCC I/O7R I/O8R I/O9R NC
3243 drw 02
NOTES: 1. A14X is a NC for IDT709269. 2. All VCC pins must be connected to power supply. 3. All GND pins must be connected to ground supply. 4. Package body is approximately 14mm x 14mm x 1.4mm 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking.
2 6.42
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Pin Names
Left Port CE0L, CE1L R/WL OEL A0L - A14L(1) I/O0L - I/O15L CLKL UBL LBL ADSL CNTENL CNTRSTL FT/PIPEL Right Port CE0R, CE1R R/WR OER A0R - A14R(1) I/O0R - I/O15R CLKR UBR LBR ADSR CNTENR CNTRSTR FT/PIPER VSS GND Names Chip Enables (3) Read/Write Enable Output Enable Address Data Input/Output Clock Upper Byte Select(2) Lower Byte Select(2) Address Strobe Counter Enable Counter Reset Flow-Through/Pipeline Power Ground
3243 tbl 01
NOTES: 1. A14x is a NC for IDT709269. 2. LB and UB are single buffered regardless of state of FT/PIPE. 3. CEo and CE1 are single buffered when FT/PIPE = VIL, CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.
Truth Table I--Read/Write and Enable Control(1,2,3)
OE X X X X X X L L L H CLK X CE0 H X L L L L L L L L CE1 X L H H H H H H H H UB X X H L H L L H L L LB X X H H L L H L L L R/W X X X L L L H H H X Upper Byte I/O8-15 High-Z High-Z High-Z DIN High-Z DIN DOUT High-Z DOUT High-Z Lower Byte I/O0-7 High-Z High-Z High-Z High-Z DIN DIN High-Z DOUT DOUT High-Z Mode Deselected--Power Down Deselected--Power Down Both Bytes Deselected Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled
3243 tbl 02
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal.
6.42 3
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Truth Table II--Address Counter Control(1,2)
External Address An X X X Previous Internal Address X An An + 1 X Internal Address Used An An + 1 An + 1 A0 CLK ADS L(4) H H X CNTEN X L
(5)
CNTRST H H H L(4)
I/O(3) DI/O (n) DI/O(n+1) DI/O(n+1) DI/O(0) External Address Used
MODE
Counter Enabled--Internal Address generation External Address Blocked--Counter disabled (An + 1 reused) Counter Reset to Address 0
3243 tbl 03
H X
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE0, CE1, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
Recommended DC Operating Recommended Operating (1) Conditions Temperature and Supply Voltage
Grade Commercial Industrial Ambient Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V VCC 5.0V + 10% 5.0V + 10%
3243 tbl 04
Symbol VCC GND VIH VIL
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage
Min. 4.5 0 2.2 -0.5
(2)
Typ. 5.0 0
____ ____
Max. 5.5 0 6.0
(1)
Unit V V V V
3243 tbl 05
NOTES: 1. This is the parameter TA. This is the "instant on" case temperature.
0.8
NOTES: 1. VTERM must not exceed VCC + 10%. 2. VIL > -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings(1)
Symbol VTERM
(2)
Capacitance(1)
Unit V
Rating Terminal Voltage with Respect to GND TemperatureUnder Bias Storage Temperature Junction Temperature DC Output Current
Commercial & Industrial -0.5 to +7.0
(TA = +25C, f = 1.0MHz)
Symbol CIN COUT
(2)
Parameter Input Capacitance Output Capacitance
Conditions(2) VIN = 0V VOUT = 0V
Max. 9 10
Unit pF pF
3243 tbl 07
TBIAS TSTG TJN IOUT
-55 to +125 -65 to +150 +150 50
o o o
C C C
NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. COUT also references CI/O.
mA
3243 tbl 06
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%. 3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselect.
4 6.42
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range (VCC = 5.0V 10%)
709279/69S/L Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current
(1)
Test Conditions VCC = 5.5V, VIN = 0V to VCC CE0 = VIH or CE1 = VIL, VOUT = 0V to VCC IOL = +4mA IOH = -4mA
Min.
___ ___ ___
Max. 10 10 0.4
___
Unit A A V V
3243 tbl 08
Output Leakage Current Output Low Voltage Output High Voltage
2.4
NOTE: 1. At VCC < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) (VCC = 5V 10%)
709279/69X6 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition CEL and CER= VIL Outputs Disabled f = fMAX(1) Version COM'L IND COM'L IND CE"A" = VIL and CE"B" = VIH(3) Active Port Outputs Disabled, f=fMAX(1) Both Ports CER and CEL > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(2) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Disabled, f = fMAX(1) COM'L IND COM'L IND COM'L IND S L S L S L S L S L S L S L S L S L S L Typ.(4) 270 270
____ ____
709279/69X7 Com'l Only Typ. (4) 250 250
____ ____
709279/69X9 Com'l Only Typ. (4) 210 210
____ ____
Max. 585 525
____ ____
Max. 490 440
____ ____
Max. 390 350
____ ____
Unit mA
ISB1
Standby Current (Both Ports - TTL Level Inputs)
CEL = CER = VIH f = fMAX(1)
80 80
____ ____
205 175
____ ____
65 65
____ ____
170 145
____ ____
50 50
____ ____
135 115
____ ____
mA
ISB2
Standby Current (One Port - TTL Level Inputs)
180 180
____ ____
405 360
____ ____
160 160
____ ____
340 295
____ ____
140 140
____ ____
270 240
____ ____
mA
ISB3
Full Standby Current (Both Ports CMOS Level Inputs)
1.0 0.2
____ ____
15 5
____ ____
1.0 0.2
____ ____
15 5
____ ____
1.0 0.2
____ ____
15 5
____ ____
mA
ISB4
Full Standby Current (One Port CMOS Level Inputs)
170 170
____ ____
395 340
____ ____
150 150
____ ____
330 290
____ ____
130 130
____ ____
245 225
____ ____
mA
NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VCC = 5V, TA = 25C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port. 6. 'X' in part numbers indicate power rating (S or L).
3243 tbl 09
6.42 5
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) (VCC = 5V 10%)
709279/69X12 Com'l & Ind Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition CEL and CER= VIL Outputs Disabled f = fMAX(1) Version COM'L IND CEL = CER = VIH f = fMAX(1) COM'L IND CE"A" = VIL and CE"B" = VIH(3) Active Port Outputs Disabled, f=fMAX(1) Both Ports CER and CEL > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(2) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Disabled, f = fMAX(1) COM'L IND COM'L IND COM'L IND S L S L S L S L S L S L S L S L S L S L Typ. (4) 200 200 200 200 50 50 50 50 130 130 130 130 1.0 0.2 1.0 0.2 120 120 120 120 Max. 345 305 380 340 110 90 125 105 230 200 245 215 15 5 15 5 205 185 220 200 709279/69X15 Com'l Only Typ. (4) 190 190
____ ____
Max. 325 285
____ ____
Unit mA
ISB1
Standby Current (Both Ports - TTL Level Inputs)
50 50
____ ____
110 90
____ ____
mA
ISB2
Standby Current (One Port - TTL Level Inputs)
120 120
____ ____
220 190
____ ____
mA
ISB3
Full Standby Current (Both Ports CMOS Level Inputs)
1.0 0.2
____ ____
15 5
____ ____
mA
ISB4
Full Standby Current (One Port CMOS Level Inputs)
110 110
____ ____
195 175
____ ____
mA
NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VCC = 5V, TA = 25C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port. 6. 'X' in part numbers indicate power rating (S or L).
3243 tbl 09a
6 6.42
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1,2 and 3
3243 tbl 10
5V 893 DATAOUT 347 30pF DATAOUT 347
5V 893
5pF*
3243 drw 04
3243 drw 05
Figure 1. AC Output Test load.
Figure 2. Output Test Load (For tCKLZ, tCKHZ, tOLZ, and tOHZ). *Including scope and jig.
8 7 6 5 tCD1, tCD2 (Typical, ns) 4 3 2 1 0 -1
- 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance
20 40 60 80 100 120 140 160 180 200 Capacitance (pF)
3243 drw 06
,
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42 7
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3,4) (VCC = 5V 10%, TA = 0C to +70C)
709279/69X6 Com'l Only Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ tOHZ tCD1 tCD2 tDC tCKHZ tCKLZ Parameter Clock Cycle Time (Flow-Through) Clock Cycle Time (Pipelined)(2) Clock High Time (Flow-Through)(2) Clock Low Time (Flow-Through) Clock High Time (Pipelined) Clock Low Time (Pipelined) Clock Rise Time Clock Fall Time Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time R/W Setup Time R/W Hold Time Input Data Setup Time Input Data Hold Time ADS Setup Time ADS Hold Time CNTEN Setup Time CNTEN Hold Time CNTRST Setup Time CNTRST Hold Time Output Enable to Data Valid Output Enable to Output Low-Z
(1) (1) (2) (2) (2) (2)
709279/69X7 Com'l Only Min. 22 12 7.5 7.5 5 5
____ ____
709279/69X9 Com'l Only Min. 25 15 12 12 6 6
____ ____
709279/69X12 Com'l & Ind Min. 30 20 12 12 8 8
____ ____
709279/69X15 Com'l Only Min. 35 25 12 12 10 10
____ ____
Min. 19 10 6.5 6.5 4 4
____ ____
Max.
____ ____ ____ ____ ____ ____
Max.
____ ____ ____ ____ ____ ____
Max.
____ ____ ____ ____ ____ ____
Max.
____ ____ ____ ____ ____ ____
Max.
____ ____ ____ ____ ____ ____
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(2)
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____
3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0
____
4 0 4 0 4 0 4 0 4 0 4 0 4 0
____
4 1 4 1 4 1 4 1 4 1 4 1 4 1
____
4 1 4 1 4 1 4 1 4 1 4 1 4 1
____
4 1 4 1 4 1 4 1 4 1 4 1 4 1
____
6.5
____
7.5
____
9
____
12
____
15
____
2 1
____ ____
2 1
____ ____
2 1
____ ____
2 1
____ ____
2 1
____ ____
Output Enable to Output High-Z
7 15 6.5
____
7 18 7.5
____
7 20 9
____
7 25 12
____
7 30 15
____
Clock to Data Valid (Flow-Through) Clock to Data Valid (Pipelined)(2) Data Output Hold After Clock High Clock High to Output High-Z Clock High to Output Low-Z
(1)
2 2 2
2 2 2
2 2 2
2 2 2
2 2 2
9
____
9
____
9
____
9
____
9
____
(1)
Port-to-Port Delay tCWDD tCCS Write Port Clock High to Read Data Delay Clock-to-Clock Setup Time
____ ____
24 9
____ ____
28 10
____ ____
35 15
____ ____
40 15
____ ____
50 20
ns ns
3243 tbl 11
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a DC signal, i.e. steady state during operation. 4. 'X' in part number indicates power rating (S or L).
8 6.42
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL)(3,7)
tCYC1 tCH1 CLK CE0 tSC CE1 tSB UB, LB R/W tHB tSB tHB tHC tSC
(4)
tCL1
tHC
tSW tSA
tHW tHA An + 1 tCD1 tDC Qn tCKLZ
(1)
ADDRESS
(5)
An
An + 2
An + 3 tCKHZ (1)
DATAOUT
Qn + 1 tOHZ
(1)
Qn + 2 tOLZ
(1)
tDC
OE
(2)
tOE
3243 drw 07
Timing Waveform of Read Cycle for Pipelined Output (FT/PIPE"X" = VIH)(3,7)
tCYC2 tCH2 CLK CE0 tSC CE1 UB, LB tSB tHB tSB
(6)
tCL2
tHC
tSC
(4)
tHC
tHB
R/W
tSW tSA
tHW tHA An + 1 (1 Latency) tCD2 Qn tCKLZ
(1)
ADDRESS
(5)
An
An + 2 tDC Qn + 1
An + 3
DATAOUT
Qn + 2
(1)
(6)
tOHZ
tOLZ
(1)
OE
(2)
tOE
3243 drw 08
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). 7. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42 9
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
tCH2 CLK tSA ADDRESS(B1) tHA A0 tSC tHC tSC tHC tCD2 DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1 A2 A3 A4 A5 A6 Q0 tDC tCD2 tCKHZ Q1 tDC
(3)
tCYC2 tCL2
A1
A2
A3
A4
A5
A6
CE0(B1)
tCD2 Q3 tCKLZ
(3)
tCKHZ (3)
tSC tHC CE0(B2) tSC tHC tCD2 DATAOUT(B2) tCKLZ
(3)
tCKHZ (3) Q2
tCD2 tCKLZ (3)
3243 drw 09
Q4
Timing Waveform of a Bank Select Flow-Through Read(6)
tCH1 CLK tSA ADDRESS(B1) tSC tHA A0 tHC tSC tCD1 DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1 A2 A3 A4 A5 A6 D0 tDC tCD1 D1 tDC tCKLZ
(1)
tCYC1 tCL1
A1
A2
A3
A4
A5
A6
CE0(B1)
tHC tCKHZ
(1)
tCD1 D3 tCKHZ (1)
tCD1 D5 tCKLZ
(1)
tSC CE0(B2) tSC tHC
tHC
tCD1 DATAOUT(B2) tCKLZ
(1)
tCKHZ D2
(1)
tCD1 tCKLZ
(1)
tCKHZ D4
(1)
NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709279/69 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
3243 drw 09a
10 6.42
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Timing Waveform with Port-to-Port Flow-Through Read(1,2,3,5)
CLK "A" tSW R/W "A" tSA ADDRESS "A" tHA
NO MATCH
tHW
MATCH
tSD DATAIN "A"
tHD
VALID
tCCS CLK "B"
(4)
tCD1 R/W "B" tSW tSA ADDRESS "B" tHW tHA
NO MATCH
MATCH
tCWDD (4) DATAOUT "B" tDC
VALID
tCD1
VALID
tDC
3243 drw 10
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 3. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 4. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case. 5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42 11
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2 tCH2 tCL2 CLK
CE0 tSC tHC CE1 tSB UB, LB tSW tHW R/W tSW tHW tHB
ADDRESS
(4)
An tSA tHA
An +1
An + 2
An + 2 tSD tHD Dn + 2
An + 3
An + 4
DATAIN
(2)
tCD2 Qn READ
tCKHZ
(1)
tCKLZ
(1)
tCD2 Qn + 3
DATAOUT
NOP
(5)
WRITE
READ
3243 drw 11
Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCH2 CLK CE0 tSC CE1 tSB UB, LB tSW tHW R/W tSW tHW tHB tHC tCYC2 tCL2
ADDRESS
(4)
An tSA tHA
An +1
An + 2 tSD tHD
An + 3
An + 4
An + 5
DATAIN
(2)
tCD2 Qn tOHZ(1)
Dn + 2
Dn + 3
tCKLZ(1)
tCD2 Qn + 4
DATAOUT
OE READ WRITE READ
3243 drw 12
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
12 6.42
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCH1 CLK tCYC1 tCL1
CE0 tSC CE1 tSB UB, LB tSW tHW R/W tSW tHW tHB tHC
ADDRESS
(4)
tSA DATAIN
(2)
An tHA
An +1
An + 2
An + 2 tSD tHD Dn + 2
An + 3
An + 4
tCD1 Qn tDC READ
tCD1 Qn + 1 tCKHZ (5) NOP
(1)
tCD1 Qn + 3 tCKLZ WRITE
(1)
tCD1
DATAOUT
tDC READ
3243 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1 tCH1 tCL1 CLK CE0 tSC tHC CE1 tSB UB, LB tSW tHW R/W ADDRESS
(4)
tHB
tSW tHW An tHA An +1 An + 2 tSD tHD Dn + 2
(2)
An + 3
An + 4
An + 5
tSA DATAIN
Dn + 3
tCD1 Qn
tDC
tOE tCD1
(1)
tCD1 Qn + 4 tDC
DATAOUT
tOHZ OE READ
(1)
tCKLZ
WRITE
READ
3243 drw 14
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42 13
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2 CLK tSA ADDRESS tHA tCYC2 tCL2
An tSAD tHAD
ADS
tSAD tHAD
CNTEN tCD2 DATAOUT Qx - 1(2) Qx tDC READ EXTERNAL ADDRESS READ WITH COUNTER Qn
tSCN tHCN
Qn + 1
Qn + 2(2)
Qn + 3
COUNTER HOLD
READ WITH COUNTER
3243 drw 15
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
tCH1 CLK tSA ADDRESS tHA tCYC1 tCL1
An tSAD tHAD
ADS
tSAD tHAD tSCN tHCN
CNTEN tCD1 DATAOUT Qx(2) tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER
3243 drw 16
Qn
Qn + 1
Qn + 2
Qn + 3(2)
Qn + 4
NOTES: 1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks.
14 6.42
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs)(1)
tCH2 CLK tSA ADDRESS tHA An tCYC2 tCL2
INTERNAL(3) ADDRESS tSAD tHAD ADS
An(1)
An + 1
An + 2
An + 3
An + 4
CNTEN tSD tHD DATAIN Dn WRITE EXTERNAL ADDRESS Dn + 1 Dn + 1 Dn + 2 Dn + 3 Dn + 4
WRITE WRITE WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
3243 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCH2 CLK tSA tHA
(4)
tCYC2 tCL2
ADDRESS INTERNAL(3) ADDRESS R/W ADS CNTEN tSRST tHRST CNTRST DATAIN
(5)
An Ax(6) tSW tHW
An + 1
An + 2
0
1
An
An + 1
tSD
tHD D0 Q0 Q1 READ ADDRESS n READ ADDRESS n+1
3243 drw 18
DATAOUT COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1
Qn
NOTES: 1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 2. CE0, UB, LB = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles are shown here simply for clarification. 7. CNTEN = VIL advances Internal Address from `An' to `An +1'. The transition shown indicates the time required for the counter to advance. The `An +1'Address is written to during this cycle.
6.42 15
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
A Functional Description
The IDT709279/69 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT709279/69's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are required with CE0 LOW and CE1 HIGH to re-activate the outputs.
Depth and Width Expansion
The IDT709279/69 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT709279/69 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 32-bit or wider applications.
A15/A14(1)
IDT709279/69
CE0 CE1 VCC
IDT709279/69
CE0 CE1 VCC
Control Inputs
Control Inputs
IDT709279/69
CE1 CE0
IDT709279/69
CE1 CE0
,
Control Inputs
Control Inputs
3243 drw 19
Figure 4. Depth and Width Expansion with IDT709279/69
CNTRST CLK ADS CNTEN R/W OE
NOTE: 1. A14 is for IDT709269.
16 6.42
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX Device Type A Power 99 Speed A Package A Process/ Temperature Range
Blank I(1)
Commercial (0C to +70C) Industrial (-40C to +85C) 100-pin TQFP (PN100-1) 108-pin PGA (G108-1)
PF G
6 7 9 12 15
Commercial Commercial Commercial Commercial Commercial
Only Only Only & Industrial Only
Speed in nanoseconds
S L
Standard Power Low Power
,
709279 512K (32K x 16-Bit) Synchronous Dual-Port RAM 709269 256K (16K x 16-Bit) Synchronous Dual-Port RAM
3243 drw 20
NOTES:
1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office.
Ordering Information for Flow-through Devices
Old Flow-through Part 70927S/L20 70927S/L25 70927S/L30 New Combined Part 709279S/L9 709279S/L12 709279S/L15
3243 tbl 12
IDT Clock Solution for IDT709279/69 Dual-Port
Dual-Port I/O Specitications IDT Dual-Port Part Number Voltage I/O Input Capacitance Clock Specifications Input Duty Cycle Requirement 40% Maximum Frequency Jitter Tolerance IDT PLL Clock Device IDT Non-PLL Clock Device 49FCT805T 49FCT806T 74FCT807T
3243 tbl 13
709279/69
5
TTL
9pF
100
150ps
FCT88915TT
6.42 17
IDT709279/69S/L High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Datasheet Document History
12/9/98: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Pages 13 & 14 Updated timing waveforms Page 15 Added Depth and Width Expansion section Changed drawing format Page 3 Deleted note 6 for Table II Replaced IDT logo Combined Pipelined 709279 family and Flow-through 70927 family offerings into one data sheet Changed 200mV in waveform notes to 0mV Added corresponding part chart with ordering information Page 1 Inserted diamond in copy Page 4 Changed information in Truth Table II, Increased storage temperature parameter, clarified TA parameter Page 5 Changed DC Electrical parameters-changed wording from "Open" to "Disabled" Page 16 Fixed typeface in heading Added Industrial Temperature Ranges and removed related notes Pages 1, 16 and Page Header Removed Preliminary status Page 5 & 7 Removed Industrial Temperature Ranges for 15ns speed from DC and AC Electrical Characteristics Page 16 Removed Industrial Temperature from 15ns speed in ordering information Consolidated multiple devices into one datasheet Page 2 Added date revision to pin configuration Page 4 Added Junction Temperature to Absolute Maximum Ratings Table Added Ambient Temperature footnote Page 5 & 6 Added 6ns & 7ns speed DC power numbers to the DC Electrical Characteristics Table Page 8 Added 6ns & 7ns speed AC timing numbers to the AC Electrical Characteristics Table Page 17 Added 6ns & 7ns speed grades to ordering information Added IDT Clock Solution Table Page 1 & 18 Replaced old logo with new TM logo
06/03/99: 11/10/99: 03/31/00: 05/24/00:
08/24/01: 06/21/04:
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-611 6 fax: 408-492-8674 www.idt.com
18 6.42
for Tech Support: 831-754-4613 DualPortHelp@idt.com
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